SEMI International Standards
SEMI New Activity Report Form (SNARF)

Activity Number: 5155
SNARF for: New Standard: Guide for Building Information Modeling (BIM) for Semiconductor Capital Equipment

Originating Global Technical Committee: Facilities
Originating Technical Committee Region: North America
Task Force in which work is to be carried out: Building Information Modeling (BIM) for Semiconductor Capital Equipment Task Force

1. Rationale: Semiconductor manufacturers are asking equipment suppliers to provide input for Building Information Modeling (BIM) software and the industry needs a standard format that will work with multiple different software applications (there are at least three software companies that work in this space). This is the latest trend in facilities planning. Basically, it is a 3D model (shell only) of a piece of capital equipment with interconnect information (water, power, gas, exhaust, etc) defined in the model. The model needs to reflect the true dimensions of the tool and show the x, y, and z location of each interface point. It is also expected to contain information about idle, typical, and maximum usage of each interface point similar to what is currently defined in SEMI E6. This allows the user to build virtual models of their entire fab, optimize layouts, and plan all of the facilities requirements (routing and sizing of all of the equipment supplies). The benefit of BIM to the semiconductor manufacturers is large when designing new fabs or optimizing existing fabs and this effort is being driven by some of the largest semiconductor companies. With a common format that works for all semiconductor manufacturers and all BIM software, the equipment manufacturers will only have to create one BIM model per equipment configuration. It can take several hundred man hours to build such a model and this would become impractical without a common format.
Rate the Estimated Effect on the Industry
2: Major effect on an industry sector - identify the relevant sector

Rate the Estimated Technical Difficulty of the Activity
II: Some Difficulty - Disagreements on known requirements exist but developing consensus is possible

2. Scope:
a: Define the areas to be covered or addressed by this activity or document:
1. This Guide would be applicable to all semiconductor wafer processing equipment (i.e. deposition, etch, inspection, track, implant, etc).
2. The Guide would define a digital format that can be easily exported from a wide array of 3D modeling programs and imported into any of the BIM software packages.
3. The Guide would define a set of required interconnects with defined location tolerances, defined features, and defined terminology.
4. The Guide will define a set of required support data for each interconnect point (ie idle, typical, max consumption).

b: Expected result of activity
New Standard

3. Projected Timetable for Completion:
a: General Milestones
a. Activity Start: 03/01/2011b. 1st Draft by: 07/01/2011
c. Preballot by: d. Technical Ballot by: 11/01/2011
e. Committee Approval By:03/01/2012

Safety Considerations:
The resulting document is expected NOT to be a Safety Guideline

Intellectual Property Considerations:
a. In complying with the standard or safety guideline to be developed, the use of patented technology or a copyrighted item(s) is NOT required
b. The body of the standard and any appendices or related information sections will NOT include copyrighted material

Comments, Special Circumstances: None.

Approval: Activity approved by Committee/GCS on March 29, 2011