SEMI International Standards
Technical Committee Charter

Charter of Global 3D Packaging and Integration Committee

To explore, evaluate, discuss, and create consensus-based specifications, guidelines, test methods, and practices that, through voluntary compliance, will:

      • include the materials, piece parts, and interconnection schemes, and unique packaging assemblies that provide for the communication link between the semiconductor chip and the next level of integration, either single- or multi-chip configurations. It relates to the technologies for heterogeneous and other multi-chip packaging such as Fan-out/Fan-in Wafer Level Packaging, Panel Level Packaging, Three-Dimensional Stacking IC, device embedded packaging, flexible electronics technology
      • promote mutual understanding and improved communication between users and suppliers, equipment, automation systems, devices, and services
      • enhance the manufacturing efficiency, capability and shorten time-to-market and reduce manufacturing cost

Scope:

The 3D Packaging and Integration Committee develops standards for semiconductor devices, including processed wafers, chips, or multi-chip configurations to the next level of integration, either in single- or multi-chip configurations
      • materials needed for 3D applications, including prime silicon and glass wafers, temporary and permanent bonding material, specifications needed for processed wafers and/or chips to enter an integration step, etc.
      • the materials related to the elements of, interconnection schemes, and unique packaging assemblies that provide for the communication link between device and packaging
      • the technologies for heterogeneous and other multi-chip packaging such as Fan-out/Fan-in Wafer Level Packaging, Panel Level Packaging, Three-Dimensional Stacking IC, device embedded packaging, and flexible electronics technology
      • metrologies to support these 3D integration and packaging technologies