SEMI International Standards
Date Prepared: 11/06/2018
Revised (if Applicable):

Name of Task Force (TF): Voltage Sag Immunity Task Force

Global Technical Committee: Facilities
Originating Technical Committee Region: North America

1. Charter: (State the objective of the proposed TF.)
SEMI F47 requires voltage sag immunity levels for single-phase and two-phase voltage sag events. Since the implementation of SEMI F47, the vulnerability of semiconductor manufacturing to voltage sags has improved significantly. However, semiconductor manufacturers have realized that they continue to experience significant product loss and downtime due to three-phase voltage sag events. Three-phase voltage sag testing was not included in the SEMI F47 standard but make up to 20 percent of voltage sags according to recent studies(*1).

The key objectives of this task force are to review the characteristics of the power quality events that are still causing semiconductor plant process downtime, take a new look at the sensitivities in the process equipment, and to determine any potential adjustments to equipment design, facility design, utility systems or standards to further reduce voltage sag induced losses by the semiconductor industry. This important work will help utilities, semiconductor manufacturers, and tool equipment providers to better understand the tolerance and susceptibility of today’s generation of semiconductor processing tools and then to develop effective strategies to improve uptime and lower product losses due not only to single-phase (Type I) and two-phase (Type II) voltage sag events but for three-phase (Type III) events as well(*2).

(*1) Per CIGRE C4.110 Voltage Sag Working Group Report and the EPRI TPQ/DPQ III study, up to 20 percent of voltage sags are three-phase in nature..
(*2) Recent Working Groups such as CIGRE C4.110 and IEEE Std. 1668-2017 “Recommended Practice for Voltage Sag and Short Interruption Ride- Through Testing for End-Use Electrical Equipment Rated Less than 1000 V” refer single, two, and three-phase voltage sag events as Type I, Type II, and Type III, respectively..

2. Scope: (Define the specific activities that the TF will conduct.)
The proposed task force activities present a systematic and logical approach to understanding the related voltage sag issues and to determining feasible solutions. The 24-month plan of activities is outlined as follows.

Task 1: Review Existing SEMI F47-0706 Requirements with respect to three-phase voltage sags.
This effort will review how tools are tested via the current revision of the SEMI F47 standard. The recommended and allowable test vectors and implications of these will be reviewed and documented. The IEEE Std. 1668-2017 recommended test methods and immunity levels will be reviewed as well with the working group. This task will culminate with a WebEx presentation of the findings.

- Estimated Schedule for Task 1 is 2 months

Task 2: Baseline Voltage Sags Causing Downtime at Semiconductor Fabs.

Since the inception of SEMI F47, many equipment providers have hardened their designs to make the tools more robust to Type I and Type II voltage sag events per SEMI F47. However, semiconductor fabs are noting that some tool sets are not able to survive minor three-phase voltage sags. The objective of this task is to work with tool suppliers, semiconductor fabs and the electric utilities to base-line the power quality events that are causing the continued downtime. The more granular this data collection effort, the better the outcome of the analysis. The Task Force looks to receive power quality data from participating tool suppliers, semiconductor fabs and utilities in order to perform analytics on the characteristics of the voltage sags along with correlations of tool downtime. The effort will culminate with a report that details the voltage sag type findings and correlations to tool shutdowns. Furthermore, the report will propose a target for Type III voltage sags immunity based on the correlated data. Locations of the sites were the power quality data is received and the tool specifics (make/model information) will be presented generically in this task force report to protect confidentiality.

- Estimated Schedule for Task 2 is 6 months

Task 3: Baseline Type III Sag Immunity of Select Tools.

This task will begin with reviewing existing tool specification with respect to three-phase voltage range tolerance. Working with the tool manufacturers, it is expected that a subset of tools will be characterized against Type I, II, and III voltage sags in either the tool manufacturer locations or within semiconductor fabs themselves. The proposed Type III voltage sag immunity target from Task 2 will be evaluated as well. The outcome of this work will provide critical information with respect to the voltage sag robustness of the tool sets with respect to Type I, II, and III voltage sags and define gaps between the actual immunity level and the proposed target. When possible mitigation strategies may be tested simultaneously against the defined voltage sag immunity targets. The report out for this effort will be presented generically with respect to tool specifics (make/model information) to protect confidentiality.

- Estimated Schedule for Task 3 is 6 months

Task 4: Determine Viable Mitigation Strategies.

Based on results from Task 3, viable voltage sag mitigation strategies will be explored for hardening equipment to meet the voltage sag immunity target for Type III events. Viable solutions will be explored at component, tool, facility, and utility levels and will evaluate both technical and economic considerations at each level. Where possible, this task will demonstrate via case studies from existing applications or new testing the effective mitigation strategies to provide the targeted immunity including Type III voltage sag events. The report out for this effort will be presented generically with respect to tool specifics (make/model information) to protect confidentiality.

- Estimated Schedule for Task 4 is 6 months

Task 5: Communicate Findings of Task Force.

Technical transfer of the general findings from the task force effort will be presented in technical papers, periodic webcasts, and workshops per the direction of the task force. This effort will happen in congruence with the other task force activities.

- Estimated Schedule for Task 5 is 2 months after completion of Tasks 1 through 4.

Task 6: Provide Recommendations to update SEMI F47 standard accordingly to reflect findings of the Task Force.

Based on the learnings form the task force efforts, recommendations will be made for any required modifications to SEMI F47-0706 or related guidelines SEMI F49-0200 (Reapproved 1213), Guide for Semiconductor Factory Systems Voltage Sag Immunity, and SEMI F50-0200 (Reapproved 1213), Guide for Electric Utility Voltage Sag Performance for Semiconductor Factories.

- Estimated Schedule for Task 6 is 2 months from completion of Tasks 1 through 5.

3. Formal linkages with TFs in other Regions/Locales: (Show each associated TF and its parent global technical committee; indicate nature of relationship – global TF, observer TF, etc.)

4. Formation Date:(TF formed on)

Task Force formed on: 11/06/2018
Task Force approved by Committee/GCS on: 11/06/2018