SEMI International Standards
Date Prepared: 11/07/2017
Revised (if Applicable): 07/11/2019

Name of Task Force (TF): Panel Level Packaging (PLP) Panel Task Force

Global Technical Committee: 3D Packaging and Integration
Originating Technical Committee Region: North America

1. Charter: (State the objective of the proposed TF.)
Panel level processing (PLP) technology is an enhanced wafer-level packaging technology, embedding die in a substrate which is patterned to allow higher density of IOs than would otherwise be supported by the chip size.

A number of different formats – including circular and rectangular (including square) – have been proposed for the substrates into which the die are embedded. In the case of panels, there have been a large number of different rectangular/square sizes. This wide selection of formats is delaying the wider acceptance of panel level packaging (PLP) technologies, as the tools must be customized for each different aspect ratio.

This Task Force will focus on the development of standards for PLP, with focus on panel dimensions. The Task Force will consider other parameters as suggested by the wider community as being appropriate for standardization.

2. Scope: (Define the specific activities that the TF will conduct.)
This Task Force will develop one or more standards focusing on PLP applications, focusing on parameters such as
Thickness range
ID marking and orientation
Edge exclusion
Geometric parameters, such as total thickness variation (TTV), bow, warp, etc.

3. Formal linkages with TFs in other Regions/Locales: (Show each associated TF and its parent global technical committee; indicate nature of relationship – global TF, observer TF, etc.)

4. Formation Date:(TF formed on)

Task Force formed on: 11/07/2017
Task Force approved by Committee/GCS on: 11/07/2017

At SEMICON West 2019 Meetings, the TF name was changed from "Fan-Out Panel Level Packaging (FO-PLP) Panel Task Force" to "Panel Level Packaging (PLP) Panel Task Force" and the charter and scope to reflect that change.