Activity Number: 5604
SNARF for: Line Item Revision to SEMI M1-0114, Specification for Polished Single Crystal Silicon Wafer and SEMI M20-0110, Practice for Establishing a Wafer Coordinate System (Re: Addition of Notchless 450 mm Wafers)
SEMI International Standards
SEMI New Activity Report Form (SNARF)
1. Rationale: Eliminating the wafer notch requires its replacement by a fiducial mark scribed on the back of the wafer. The proposed change will improve the wafer symmetry, increase the surface utilization. The major task is to get consensus on the mark design and positions, considering readability and potential impact on wafer integrity through the entire IC manufacturing process
Rate the Estimated Effect on the Industry
1: Major effect on entire industry or on multiple important industry sectors
Rate the Estimated Technical Difficulty of the Activity
II: Some Difficulty - Disagreements on known requirements exist but developing consensus is possible
a: Define the areas to be covered or addressed by this activity or document:
Add a new category for 450 mm notchless wafer to to SEMI M1 together with the necessary text and figures in Tables 1, 9, and R1-1, and ¶¶2.2, and 22.214.171.124, Note 4, ¶¶126.96.36.199 through 188.8.131.52.3, and Figures 6 through 9. Because the M1 revision to add the notchless wafer includes considerable reference to the angular coordinate system of SEMI M20, it is necessary to slightly revise that standard by adding reference to orientation fiducial marks in the captions to Figures 1 and 2. In addition, it was found that the equation was omitted from ¶7.1.9 when the current edition was published by SEMI in 2010, so this needs to be corrected.
b: Expected result of activity
Revision to an existing Standard/Guideline
3. Projected Timetable for Completion:
|Originating Global Technical Committee: Silicon Wafer|
|Originating Technical Committee Region: North America|
|Task Force in which work is to be carried out: International 450 mm Wafer Task Force|
|a: General Milestones|
|a. Activity Start: 07/01/2013||b. 1st Draft by: 12/01/2013|
|c. Preballot by: ||d. Technical Ballot by: 04/30/2014|
|e. Committee Approval By:07/08/2014|
The resulting document is expected NOT to be a Safety Guideline
Intellectual Property Considerations:
a. In complying with the standard or safety guideline to be developed, the use of patented technology or a copyrighted item(s) is NOT required
b. The body of the standard and any appendices or related information sections will NOT include copyrighted material
Comments, Special Circumstances: In reviewing the SNARF, John Valley (Sun Edison) informed the committee that there is a published patent “Production of Notchless Wafer (publication number US5993292 A)”. It was informed to the committee.
According to Mike Goldstein (Intel), there are number of ways of producing notchless wafer. The referenced patent is one of the methods, not THE only method of producing notchless wafer.
Pinyen Lin (G450C), the main driver for the 450 mm notches wafer standard, is aware of the patent.
In moving forward, it is the best to the knowledge of the NA Silicon Wafer committee, the use of patented technology or a copyrighted item(s) is NOT required for the activity in question. Also, it was assumed that the activity being proposed by G450C will not be required the use of patented technology.
Approval: Activity approved by Committee/GCS on April 1, 2014
Copyright ©2014 Semiconductor Equipment and Materials International (SEMI®). All rights reserved.