SEMI International Standards
TASK FORCE ORGANIZATION FORM (TFOF)
Date Prepared:
05/22/2011
Revised (if Applicable):
Name of Task Force (TF):
International Nanoimprint Lithography Task Force
Global Technical Committee:
Micropatterning
Originating Technical Committee Region:
Europe
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1. Charter:
(State the objective of the proposed TF.)
Advances in academic research and early stage developments in commercialization of micro / nano patterned devices via print and imprint technologies have generated industry attention due to its opportunities for process simplification and potential for cost efficient device manufacturing.
The International Technology Roadmap for Semiconductors (ITRS) has adopted nanoimprint lithography (NIL) as a contending Next Generation Lithography (NGL) for technology nodes ≤32nm and standardization efforts are under way amongst others supported by the National Institute of Standards and Technology (NIST), and industry consortia such as Molecular Imprints, Inc., Sematech International, Nanoimprint Process Solutions (NiPS) and NILCom«.
Since a noticeable install base for NIL processing equipment from various suppliers promote multiple processes, template / stamp and substrate formats, efforts are required to enable a clear communication within the industry on processes (hot embossing, SFIL, etc.) and their respective template/stamp and substrate requirements. To date it is estimated that there are over 160 system installed for R&D in nanoprint and nanoimprint technologies with an anticipated annual system growth of ~15%. Market research firms estimate that NIL related equipment sales may reach $35mio in 2007.
This task force sets out to collect, evaluate and define the infrastructure for NIL template design and specification to accelerate commercialization and help to make NIL a reality in manufacturing.
Yole Development, "The MEMS equipment market is 6 times bigger compared to the equipment market for nanotechnologies", MicroNews 38, page 16, July 2005
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2. Scope:
(Define the specific activities that the TF will conduct.)
1. Examine IP free, patented and copyrighted items regarding template fabrication and utilization
2. Definition of existing infrastructure
In reference to ITRS Mask Fabrication and Process Control:
Defect free 1x masks
Timeliness and capability of 1x mask equipment
Mask process control methods and yield enhancement
3. Identification of applicable SEMI standards
4. Template form factor
5. Test Structures (existing patterns to establish benchmark and comparison)
6. Alignment Target (type of pattern, contrast, Chrom layer?)
7. Cutting and Polishing (edge roughness, tensions/stress, contamination (protective seal), cleaning, finish, final dimension)
8. Inspection (100%) (transparent template, test imprint)
In reference to ITRS Metrology and Defect Inspection:
Resolution and precision for critical dimensions (limits) including metrology
9. Defects
10. Cleaning
11. Release Layer
12. Processing
13. Evaluation (measure imprint result and derive conclusion for template, develop processing matrix, monitor pattern, determine relation between monitor features and device features)
14. Repair (repair transparent substrates (similar to phase shift mask, positioning issues)
15. Handling
16. Transport (How to fix, conditions and environemental influence, standard size packaging)
17. Ordering specification
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3. Formal linkages with TFs in other Regions/Locales:
(Show each associated TF and its parent global technical committee; indicate nature of relationship – global TF, observer TF, etc.)
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4. Formation Date:
(TF formed on)
Task Force formed on:
10/05/2007
Task Force approved by Committee/GCS on:
05/14/2011
5. Comments
None.
